Title of the talk:
" MODELING AND SIMULATION OF ATOMICALLY THIN TRANSISTORS "
Dr. Yogesh Singh Chauhan
Editor of IEEE Transactions on Electron Devices
Technical Program Committee member of IEDM 2018
Department of Electrical Engineering
Indian Institute of Technology Kanpur
Kanpur, U.P. - 208016, India
Tel: +91-512-6797244 (landline), Fax: +91-512-2590063
Owing to the rapid market development of portable electronic devices such as notebooks and smart-phones, the feature size of CMOS must be scaled down to meet consumers' demands. The scaled transistors offer high performance, low power and low cost per transistor for an IC. But the conventional MOSFETs face lot of challenges as the feature size is being scaled down, such as random dopant fluctuation, thermal budgets and short channel effects. Extremely-thin body channel MOSFET and 2-Dimensional (2D) semiconductor channel devices, can circumvent aforementioned issues as thin body provides better electrostatic gate control on the channel to counter short channel effects. Additionally, 2D semiconductors have other advantages over conventional semiconductors, specifically, an atomically smooth and dangling bond-free surface and a uniform thickness. To assess the impact of alternative channel materials on the thin body transistor and circuit performance, numerical simulation and compact modeling play vital role. In this talk, I will discuss on the modeling, simulation and electrical behavior of atomically thin transistors.
Yogesh Singh Chauhan is currently an Associate Professor in the Department of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur, U.P. - 208016, India. He is also the Editor of IEEE Transactions on Electron Devices and a Technical Program Committee member of IEDM 2018.